The present invention relates to a method of fabricating silicate dielectrics that have superior electrical properties compared with SiO2 and to semiconductor structures such as field effect transistors (FETs) which contain the same.
In the field of semiconductor transistor manufacturing, the formation of a gate dielectric is a critical step in the fabrication process. It is highly desirable in such art to reduce the leakage current that is caused by electron tunneling through the SiO2 layer conventionally used as the gate dielectric.
One approach to improving the electrical characteristics of the gate dielectric is to use an alternative dielectric material with a larger dielectric constant than SiO2; allowing the use of a greater physical thickness for the gate insulator.
Numerous transition metal oxides have larger dielectric constants than SiO2; however maintaining compatibility with standard silicon processing is a tremendous challenge.
A complete discussion on the above compatibility problem is provided by K. J. Hubbard, et al. xe2x80x9cThermodynamic Stability of Binary Oxides in Contact With Silicon,xe2x80x9d J. Mater. Res., Vol. 11, No. 11, pp. 2757-2776 (1996).
There is thus a need for developing a method of fabricating dielectric materials having dielectric constants greater than SiO2 which maintain compatibility with standard silicon processing. There is also a need for developing a method of fabricating dielectric materials in which the electrical properties of the dielectric are superior to SiO2 dielectrics heretofore known.
One object of the present invention is to provide a method of fabricating a dielectric material which maintains compatibility with standard silicon processing.
Another object of the present invention is to provide a method of fabricating a dielectric material having a dielectric constant greater than SiO2.
A further object of the present invention is to provide a method of fabricating a dielectric material which can significantly reduce the leakage current normally associated with an SiO2 dielectric.
A yet further object of the present invention is to provide a simple method of forming a silicate/SiO2 gate stack with a self-limiting oxide equivalent thickness.
These and other objects and advantages are obtained in the present invention by oxidizing a metal oxide layer that is formed on a silicon substrate under conditions sufficient to convert the metal oxide layer into a silicate by intermixing with the underlying silicon, while simultaneously oxidizing the underlying silicon. Specifically, the method of the present invention comprises the steps of:
(a) forming a metal oxide layer on a silicon-containing material; and
(b) heating the metal oxide layer in the presence of an oxidizing agent under conditions so as to convert the metal oxide layer into a metal silicate layer while simultaneously oxidizing a portion of the silicon-containing material underlying the metal silicate layer.
In one embodiment of the present invention, the method of the present invention further comprises annealing the metal silicate layer produced in step (b) above.
In yet another embodiment of the present invention, an elemental metal layer is formed on the silicon-containing material and thereafter step (b) is performed. In this embodiment, the oxidation step, step (b), is carried out under conditions that are effective in transforming the metal layer to a metal oxide layer and then to a metal silicate layer.
Another aspect of the present invention relates to semiconductor structures such as capacitors and transistors which include at least the metal silicate produced by the method of the present invention therein. Specifically, the inventive semiconductor structures comprise at least a metal silicate that is formed on a silicon oxide layer, said silicon oxide layer being formed on a Si-containing substrate.
Another aspect of the present invention relates to a field effect transistor which comprises a Si-containing semiconductor substrate;
spaced apart source and drain regions in said substrate, said spaced apart source/drain regions defining a channel region;
a dielectric layer above said channel region, said dielectric layer including a first layer of a metal silicate; and
a gate electrode formed over said dielectric layer.